It is recognized that an effective method of fabricating semiconductor devices involves performing two or more successive dopings into a semiconductor layer to thereby, for instance, establish a region of one type conductivity within a second region of an opposite type conductivity which is itself situated in a layer of one type conductivity. It is desirable to align the various regions in a desired relationship to allow the fabricated device to function properly. Practically, it is difficult to precisely align two regions with available semiconductor techniques and thus the fabricated device may not operate as well as it might. An example of one such device involves an insulated gate transistor in which a first region of opposite type conductivity is disposed with a second region of one type conductivity disposed within a layer of opposite type conductivity. An insulated gate electrode is disposed on the layer coextensive with a portion of the second region to provide for conduction of one type conductivity carriers between the layer and the first region.
These insulated gate transistors, however, are susceptible to operation in a non-preferred mode whereby a parasitic bipolar transistor disposed within the device may turn on in an undesired fashion, if for instance, the short between the source and base is not adequate or if the sheet resistance of the base is too low. It has been proposed to improve the sheet resistance of the base of the device by using a second deep P+ diffusion in a parasitic NPN structure to reduce the sheet resistance of the P base layer and at the same time provide good contact between a source electrode and the lightly doped P base region. This deep P+ diffusion, in combination with the lightly doped shallow base diffusion, determines the channel properties of the device.
It has been a limitation of prior insulated gate transistors that the deep P+ diffusions could not be easily fabricated because careful alignment of the source region with the base region is required to advantageously employ a deep P+ base within a device and to provide a device exhibiting a current density which is commercially acceptable. Inasmuch as a single mask has heretofore been employed to define only two separate regions, it has not been possible to precisely align two separate regions. Misalignments occur and the devices must be configured to accommodate the misalignments. Specifically, misalignment of the source region with the base region within an insulated gate transistor establishes a longer current path along the junction between the source and base regions and hence increases the voltage drop along that junction contributing to a potential breakdown across that junction. If a breakdown does occur across that junction, the parasitic transistor turns on and gate control of the device is lost. It is therefore desirable to minimize the length of the junction and the size of the device regions to avoid this undesired potential breakdown by precisely aligning the regions of the device.